diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/lower-to-ground/accessor.fir | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/lower-to-ground/accessor.fir')
| -rw-r--r-- | test/passes/lower-to-ground/accessor.fir | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir deleted file mode 100644 index c712fdc2..00000000 --- a/test/passes/lower-to-ground/accessor.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower To Ground -circuit top : - module top : - input clk : Clock - wire i : UInt<2> - wire j : UInt<32> - - wire a : UInt<32>[4] - ; CHECK: wire a{{[_$]+}}0 : UInt<32> - ; CHECK: wire a{{[_$]+}}1 : UInt<32> - ; CHECK: wire a{{[_$]+}}2 : UInt<32> - ; CHECK: wire a{{[_$]+}}3 : UInt<32> - - infer accessor b = a[i] - ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32> - j <= b - - infer accessor c = a[i] - ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32> - c <= j - - cmem p : UInt<32>[4],clk - infer accessor t = p[i] - ; CHECK: read accessor t = p[i] - j <= t - infer accessor r = p[i] - ; CHECK: write accessor r = p[i] - r <= j - -; CHECK: Finished Lower To Ground |