Pass most tests. The ones that do not pass are not expected to, yet

6 files changed, 12 insertions, 12 deletions

diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1953e39b..59352162 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -17,7 +17,7 @@ circuit MemorySearch :
     elts[4] := UInt<4>(2)
     elts[5] := UInt<4>(5)
     elts[6] := UInt<4>(13)
-    accessor elt = elts[index]
+    infer accessor elt = elts[index]
     node T_35 = bit-not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 58515110..14db8769 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -25,5 +25,5 @@ circuit Mul :
     tbl[15] := UInt<4>(9)
     node T_42 = shl(x, 2)
     node T_43 = bit-or(T_42, y)
-    accessor T_44 = tbl[T_43]
+    infer accessor T_44 = tbl[T_43]
     z := T_44
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index ee417771..3c70c670 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -22,5 +22,5 @@ circuit Rom :
     r[13] := UInt<5>(26)
     r[14] := UInt<5>(28)
     r[15] := UInt<5>(30)
-    accessor T_39 = r[addr]
+    infer accessor T_39 = r[addr]
     out := T_39
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 43f61827..4bce2bd4 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -17,7 +17,7 @@ circuit Stack :
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = bit-and(push, T_30)
       when T_31 : 
-        accessor T_32 = stack_mem[sp]
+        infer accessor T_32 = stack_mem[sp]
         T_32 := dataIn
         node T_33 = add-wrap(sp, UInt<1>(1))
         sp := T_33
@@ -30,6 +30,6 @@ circuit Stack :
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = sub-wrap(sp, UInt<1>(1))
-        accessor T_39 = stack_mem[T_38]
+        infer accessor T_39 = stack_mem[T_38]
         out := T_39
     dataOut := out
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 4e0e954c..f315aaa9 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -10,9 +10,9 @@ circuit Tbl :
     cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
-      accessor T_13 = m[i]
+      infer accessor T_13 = m[i]
       node T_14 = bits(d, 9, 0)
       T_13 := T_14
     else : 
-      accessor T_15 = m[i]
+      infer accessor T_15 = m[i]
       o := T_15
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 4d02bcf7..21030448 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,23 +13,23 @@ circuit Risc :
     cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
-    accessor inst = code[pc]
+    infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_51 = eq(rai, UInt<1>(0))
-    accessor T_52 = file[rai]
+    infer accessor T_52 = file[rai]
     node ra = mux(T_51, UInt<1>(0), T_52)
     node T_53 = eq(rbi, UInt<1>(0))
-    accessor T_54 = file[rbi]
+    infer accessor T_54 = file[rbi]
     node rb = mux(T_53, UInt<1>(0), T_54)
     wire rc : UInt<32>
     valid := UInt<1>(0)
     out := UInt<1>(0)
     rc := UInt<1>(0)
     when isWr : 
-      accessor T_55 = code[wrAddr]
+      infer accessor T_55 = code[wrAddr]
       T_55 := wrData
     else : when boot : pc := UInt<1>(0)
       else : 
@@ -46,7 +46,7 @@ circuit Risc :
         node T_61 = eq(rci, UInt<8>(255))
         when T_61 : valid := UInt<1>(1)
         else : 
-          accessor T_62 = file[rci]
+          infer accessor T_62 = file[rci]
           T_62 := rc
         node T_63 = add-wrap(pc, UInt<1>(1))
         pc := T_63