diff options
| author | azidar | 2015-04-08 11:28:29 -0700 |
|---|---|---|
| committer | azidar | 2015-04-08 11:28:29 -0700 |
| commit | e5b9f6ec710e8573ce262330731bebc7524296e5 (patch) | |
| tree | 1494853a2939b20bb2c671d3c46daa29b76ecec3 /test/passes/jacktest/vecshift.fir | |
| parent | d4fdab6950b47379137fce750e4a3a6b262e750d (diff) | |
Finished expand whens. started infer widths. added pdf for people to view
Diffstat (limited to 'test/passes/jacktest/vecshift.fir')
| -rw-r--r-- | test/passes/jacktest/vecshift.fir | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir new file mode 100644 index 00000000..9910064d --- /dev/null +++ b/test/passes/jacktest/vecshift.fir @@ -0,0 +1,24 @@ +; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s + +; CHECK: Expand Whens + +circuit VecShiftRegister : + module VecShiftRegister : + input load : UInt(1) + output out : UInt(4) + input shift : UInt(1) + input ins : UInt(4)[4] + + reg delays : UInt(4)[4] + when load : + delays.0 := ins.0 + delays.1 := ins.1 + delays.2 := ins.2 + delays.3 := ins.3 + else : when shift : + delays.0 := ins.0 + delays.1 := delays.0 + delays.2 := delays.1 + delays.3 := delays.2 + out := delays.3 +; CHECK: Finished Expand Whens |