merge

1 files changed, 14 insertions, 14 deletions

diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir
index 4d2563af..9914ea04 100644
--- a/test/passes/jacktest/vecshift.fir
+++ b/test/passes/jacktest/vecshift.fir
@@ -4,21 +4,21 @@
 
 circuit VecShiftRegister : 
   module VecShiftRegister : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when load : 
-      delays.0 := ins.0
-      delays.1 := ins.1
-      delays.2 := ins.2
-      delays.3 := ins.3
+      delays[0] := ins[0]
+      delays[1] := ins[1]
+      delays[2] := ins[2]
+      delays[3] := ins[3]
      else : when shift : 
-        delays.0 := ins.0
-        delays.1 := delays.0
-        delays.2 := delays.1
-        delays.3 := delays.2
-    out := delays.3
+        delays[0] := ins[0]
+        delays[1] := delays[0]
+        delays[2] := delays[1]
+        delays[3] := delays[2]
+    out := delays[3]
 ; CHECK: Finished Expand Whens