diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/jacktest/risc.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/jacktest/risc.fir')
| -rw-r--r-- | test/passes/jacktest/risc.fir | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 46f5a1c2..f722cf97 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -13,7 +13,8 @@ circuit Risc : cmem file : UInt<32>[256] cmem code : UInt<32>[256] - reg pc : UInt<8>,clk,reset,UInt<8>(0) + reg pc : UInt<8>,clk with : + reset => (reset,UInt<8>(0)) read mport inst = code[pc],clk node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) @@ -36,7 +37,7 @@ circuit Risc : else : node T_56 = eq(UInt<1>(0), op) when T_56 : - node T_57 = addw(ra, rb) + node T_57 = tail(add(ra, rb),1) rc <= T_57 node T_58 = eq(UInt<1>(1), op) when T_58 : @@ -49,5 +50,5 @@ circuit Risc : else : write mport T_62 = file[rci],clk T_62 <= rc - node T_63 = addw(pc, UInt<1>(1)) + node T_63 = tail(add(pc, UInt<1>(1)),1) pc <= T_63 |