diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/risc.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/risc.fir')
| -rw-r--r-- | test/passes/jacktest/risc.fir | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index a28dc5a5..fdc80ee1 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -14,7 +14,7 @@ circuit Risc : cmem file : UInt<32>[256],clk cmem code : UInt<32>[256],clk reg pc : UInt<8>,clk,reset - onreset pc := UInt<8>(0) + onreset pc <= UInt<8>(0) infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) @@ -27,28 +27,28 @@ circuit Risc : infer accessor T_54 = file[rbi] node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> - valid := UInt<1>(0) - out := UInt<1>(0) - rc := UInt<1>(0) + valid <= UInt<1>(0) + out <= UInt<1>(0) + rc <= UInt<1>(0) when isWr : infer accessor T_55 = code[wrAddr] - T_55 := wrData - else : when boot : pc := UInt<1>(0) + T_55 <= wrData + else : when boot : pc <= UInt<1>(0) else : node T_56 = eq(UInt<1>(0), op) when T_56 : node T_57 = addw(ra, rb) - rc := T_57 + rc <= T_57 node T_58 = eq(UInt<1>(1), op) when T_58 : node T_59 = shl(rai, 8) node T_60 = or(T_59, rbi) - rc := T_60 - out := rc + rc <= T_60 + out <= rc node T_61 = eq(rci, UInt<8>(255)) - when T_61 : valid := UInt<1>(1) + when T_61 : valid <= UInt<1>(1) else : infer accessor T_62 = file[rci] - T_62 := rc + T_62 <= rc node T_63 = addw(pc, UInt<1>(1)) - pc := T_63 + pc <= T_63 |