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authorazidar2015-05-27 17:15:44 -0700
committerazidar2015-05-27 17:15:44 -0700
commitb44b49e6a6589add30b5b1d89d85f2e20432a515 (patch)
tree36a70d1d330f7163fe66af1adcd126c6f92af699 /test/passes/jacktest/risc.fir
parenta2a48576534f87b28566504bb1e0c7faa493f463 (diff)
Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names
Diffstat (limited to 'test/passes/jacktest/risc.fir')
-rw-r--r--test/passes/jacktest/risc.fir4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 875498d6..4d02bcf7 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -9,8 +9,8 @@ circuit Risc :
input wrAddr : UInt<8>
input wrData : UInt<32>
- mem file : UInt<32>[256]
- mem code : UInt<32>[256]
+ cmem file : UInt<32>[256]
+ cmem code : UInt<32>[256]
reg pc : UInt<8>
on-reset pc := UInt<8>(0)
accessor inst = code[pc]