Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 29 deletions

diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
deleted file mode 100644
index 31ca30b2..00000000
--- a/test/passes/jacktest/gcd.fir
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit GCD : 
-  module GCD : 
-    input e : UInt<1>
-    input clk : Clock
-    input reset : UInt<1>
-    output z : UInt<16>
-    output v : UInt<1>
-    input a : UInt<16>
-    input b : UInt<16>
-    
-    reg x : UInt<16>,clk with :
-       reset => (reset,x)
-    reg y : UInt<16>,clk with :
-       reset => (reset,y)
-    node T_17 = gt(x, y)
-    when T_17 : 
-      node T_18 = tail(sub(x, y),1)
-      x <= T_18
-    else : 
-      node T_19 = tail(sub(y, x),1)
-      y <= T_19
-    when e : 
-      x <= a
-      y <= b
-    z <= x
-    node T_20 = eq(y, UInt<1>(0))
-    v <= T_20