diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/gcd.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/gcd.fir')
| -rw-r--r-- | test/passes/jacktest/gcd.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index c461efe3..99667b3b 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -15,13 +15,13 @@ circuit GCD : node T_17 = gt(x, y) when T_17 : node T_18 = subw(x, y) - x := T_18 + x <= T_18 else : node T_19 = subw(y, x) - y := T_19 + y <= T_19 when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x node T_20 = eq(y, UInt<1>(0)) - v := T_20 + v <= T_20 |