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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-14 11:29:55 -0700
commit271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch)
tree8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/jacktest/gcd.fir
parent0bfb3618b654a4082cc2780887b3ca32e374f455 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/jacktest/gcd.fir')
-rw-r--r--test/passes/jacktest/gcd.fir10
1 files changed, 6 insertions, 4 deletions
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index a0c1e10a..f3f12017 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -3,19 +3,21 @@
circuit GCD :
module GCD :
input e : UInt<1>
+ input clk : Clock
+ input reset : UInt<1>
output z : UInt<16>
output v : UInt<1>
input a : UInt<16>
input b : UInt<16>
- reg x : UInt<16>
- reg y : UInt<16>
+ reg x : UInt<16>,clk,reset
+ reg y : UInt<16>,clk,reset
node T_17 = gt(x, y)
when T_17 :
- node T_18 = sub-wrap(x, y)
+ node T_18 = subw(x, y)
x := T_18
else :
- node T_19 = sub-wrap(y, x)
+ node T_19 = subw(y, x)
y := T_19
when e :
x := a