Finished expand whens. started infer widths. added pdf for people to view

1 files changed, 20 insertions, 0 deletions

diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir
new file mode 100644
index 00000000..0d0f0377
--- /dev/null
+++ b/test/passes/jacktest/bundlewire.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
+
+circuit BundleWire : 
+  module BundleWire : 
+    output in : { y : UInt(32), x : UInt(32) }
+    output outs : { y : UInt(32), x : UInt(32) }[4]
+    
+    wire coords : { y : UInt(32), x : UInt(32) }[4]
+    coords.0 := in
+    outs.0 := coords.0
+    coords.1 := in
+    outs.1 := coords.1
+    coords.2 := in
+    outs.2 := coords.2
+    coords.3 := in
+    outs.3 := coords.3
+
+; CHECK: Finished Expand Whens