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| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/passes/jacktest/VendingMachine.fir | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/passes/jacktest/VendingMachine.fir')
| -rw-r--r-- | test/passes/jacktest/VendingMachine.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir index 79cebbe1..d7822a17 100644 --- a/test/passes/jacktest/VendingMachine.fir +++ b/test/passes/jacktest/VendingMachine.fir @@ -8,7 +8,8 @@ circuit VendingMachine : input clk : Clock input reset : UInt<1> - reg state : UInt<3>,clk,reset,UInt<3>(0) + reg state : UInt<3>,clk with : + reset => (reset,UInt<3>(0)) node T_22 = eq(state, UInt<3>(0)) when T_22 : when nickel : state <= UInt<3>(1) |