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authorazidar2015-04-24 17:00:01 -0700
committerazidar2015-04-24 17:00:01 -0700
commitced5ddb48843cd5b00498d1066f52c2925b142b9 (patch)
tree147be80363c183b88521e3d1f492b83939be20ba /test/passes/jacktest/Tlb.fir
parente9462f11f6cfd68d0ada3b95a7d48621970e520e (diff)
parent5a2a495ce88eec9e2e79cfbfe7f5548cede25874 (diff)
Merge branch 'master' of github.com:ucb-bar/firrtl into parser
Conflicts: TODO src/main/stanza/passes.stanza
Diffstat (limited to 'test/passes/jacktest/Tlb.fir')
-rw-r--r--test/passes/jacktest/Tlb.fir18
1 files changed, 18 insertions, 0 deletions
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
new file mode 100644
index 00000000..35442ac8
--- /dev/null
+++ b/test/passes/jacktest/Tlb.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Tbl :
+ module Tbl :
+ output o : UInt(16)
+ input i : UInt(16)
+ input d : UInt(16)
+ input we : UInt(1)
+
+ mem m : UInt(10)[256]
+ node T_12 = UInt(0, 1)
+ o := Pad(T_12,?)
+ when we :
+ accessor T_13 = m[i]
+ T_13 := Pad(d,?)
+ else :
+ accessor T_14 = m[i]
+ o := Pad(T_14,?)