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authorjackbackrack2015-04-27 17:37:42 -0700
committerjackbackrack2015-04-27 17:37:42 -0700
commit2a4f374b19e10a1571fbd2a23b30e92c9179defd (patch)
treed106c4bd0204124cdf46479e8f6ebc1e37ede3d1 /test/passes/jacktest/Tlb.fir
parentcbc928e5e80898163871b8be1b34106e5275af58 (diff)
parentd6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f (diff)
merge
Diffstat (limited to 'test/passes/jacktest/Tlb.fir')
-rw-r--r--test/passes/jacktest/Tlb.fir12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
index 35442ac8..b458ac4a 100644
--- a/test/passes/jacktest/Tlb.fir
+++ b/test/passes/jacktest/Tlb.fir
@@ -2,13 +2,13 @@
; CHECK: Done!
circuit Tbl :
module Tbl :
- output o : UInt(16)
- input i : UInt(16)
- input d : UInt(16)
- input we : UInt(1)
+ output o : UInt<16>
+ input i : UInt<16>
+ input d : UInt<16>
+ input we : UInt<1>
- mem m : UInt(10)[256]
- node T_12 = UInt(0, 1)
+ mem m : UInt<10>[256]
+ node T_12 = UInt<1>(0)
o := Pad(T_12,?)
when we :
accessor T_13 = m[i]