diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/Tbl.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/Tbl.fir')
| -rw-r--r-- | test/passes/jacktest/Tbl.fir | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir deleted file mode 100644 index 5feb71bb..00000000 --- a/test/passes/jacktest/Tbl.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! - -circuit Tbl : - module Tbl : - input clk : Clock - input reset : UInt<1> - output io : {flip wi : UInt<3>, flip ri : UInt<3>, flip we : UInt<1>, flip d : UInt<3>, o : UInt<3>} - - io.o <= UInt<1>("h00") - cmem m : UInt<3>[8] - infer mport T_12 = m[io.ri], clk - io.o <= T_12 - when io.we : - infer mport T_13 = m[io.wi], clk - T_13 <= io.d - node T_14 = eq(io.ri, io.wi) - when T_14 : - io.o <= io.d - skip - skip |