diff options
| author | azidar | 2016-01-24 16:36:13 -0800 |
|---|---|---|
| committer | azidar | 2016-01-24 16:36:13 -0800 |
| commit | 5cb43f0cb9ff16a448f8f7b76698b569d2d63125 (patch) | |
| tree | 574704c808e24bafae32c8b544725d435eeb455a /test/passes/jacktest/Tbl.fir | |
| parent | a899ff3606421467400380fc35a6035290bef791 (diff) | |
Fixed tests that broke from changing verilog backend and removing mask from write mport declaration
Diffstat (limited to 'test/passes/jacktest/Tbl.fir')
| -rw-r--r-- | test/passes/jacktest/Tbl.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 9b259d0f..f760af68 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -11,7 +11,7 @@ circuit Tbl : cmem m : UInt<10>[256] o <= UInt<1>(0) when we : - write mport T_13 = m[i],clk,UInt(1) + write mport T_13 = m[i],clk node T_14 = bits(d, 9, 0) T_13 <= T_14 else : |