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authorazidar2016-01-08 15:51:41 -0800
committerazidar2016-01-16 14:28:18 -0800
commit168843e45656b3569461f496b85def20b70779d2 (patch)
treee727b1fa3be5adacd07b865d55e0ffdffe9ee2e8 /test/passes/jacktest/Tbl.fir
parent4569194392122ae4715549b2f0b9fffff051b278 (diff)
Finished first cut at new firrtl - time for testing! Chirrtl requires masks to be specified with write and rdwr mports
Diffstat (limited to 'test/passes/jacktest/Tbl.fir')
-rw-r--r--test/passes/jacktest/Tbl.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 4ae87360..9b259d0f 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -8,12 +8,12 @@ circuit Tbl :
output o : UInt<16>
input we : UInt<1>
- cmem m : UInt<10>[256],clk
+ cmem m : UInt<10>[256]
o <= UInt<1>(0)
when we :
- infer accessor T_13 = m[i]
+ write mport T_13 = m[i],clk,UInt(1)
node T_14 = bits(d, 9, 0)
T_13 <= T_14
else :
- infer accessor T_15 = m[i]
+ read mport T_15 = m[i],clk
o <= T_15