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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-13 16:22:43 -0700
commit9b6d8514a3be860562d8d524fa425c87d1537e8a (patch)
treeca46b9703046e23068860b5c5d8d6af01296c000 /test/passes/jacktest/Tbl.fir
parent1ed6d4a47c92072b12db4b784f239071e4928049 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/jacktest/Tbl.fir')
-rw-r--r--test/passes/jacktest/Tbl.fir3
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index f315aaa9..b916e0f0 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -4,10 +4,11 @@ circuit Tbl :
module Tbl :
input i : UInt<16>
input d : UInt<16>
+ input clk : Clock
output o : UInt<16>
input we : UInt<1>
- cmem m : UInt<10>[256]
+ cmem m : UInt<10>[256],clk
o := UInt<1>(0)
when we :
infer accessor T_13 = m[i]