diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/Rom.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/Rom.fir')
| -rw-r--r-- | test/passes/jacktest/Rom.fir | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir index 382ca5c9..6e4b3cc7 100644 --- a/test/passes/jacktest/Rom.fir +++ b/test/passes/jacktest/Rom.fir @@ -6,21 +6,21 @@ circuit Rom : input addr : UInt<4> wire r : UInt<5>[16] - r[0] := UInt<5>(0) - r[1] := UInt<5>(2) - r[2] := UInt<5>(4) - r[3] := UInt<5>(6) - r[4] := UInt<5>(8) - r[5] := UInt<5>(10) - r[6] := UInt<5>(12) - r[7] := UInt<5>(14) - r[8] := UInt<5>(16) - r[9] := UInt<5>(18) - r[10] := UInt<5>(20) - r[11] := UInt<5>(22) - r[12] := UInt<5>(24) - r[13] := UInt<5>(26) - r[14] := UInt<5>(28) - r[15] := UInt<5>(30) + r[0] <= UInt<5>(0) + r[1] <= UInt<5>(2) + r[2] <= UInt<5>(4) + r[3] <= UInt<5>(6) + r[4] <= UInt<5>(8) + r[5] <= UInt<5>(10) + r[6] <= UInt<5>(12) + r[7] <= UInt<5>(14) + r[8] <= UInt<5>(16) + r[9] <= UInt<5>(18) + r[10] <= UInt<5>(20) + r[11] <= UInt<5>(22) + r[12] <= UInt<5>(24) + r[13] <= UInt<5>(26) + r[14] <= UInt<5>(28) + r[15] <= UInt<5>(30) infer accessor T_39 = r[addr] - out := T_39 + out <= T_39 |