Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 31 deletions

diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
deleted file mode 100644
index f138d00a..00000000
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit RegisterVecShift : 
-  module RegisterVecShift : 
-    input load : UInt<1>
-    input clk : Clock
-    input reset : UInt<1>
-    output out : UInt<4>
-    input shift : UInt<1>
-    input ins : UInt<4>[4]
-    
-    reg delays : UInt<4>[4],clk with :
-       reset => (reset,delays)
-    when reset : 
-      wire T_33 : UInt<4>[4]
-      T_33[0] <= UInt<4>(0)
-      T_33[1] <= UInt<4>(0)
-      T_33[2] <= UInt<4>(0)
-      T_33[3] <= UInt<4>(0)
-      delays <= T_33
-    when load : 
-      delays[0] <= ins[0]
-      delays[1] <= ins[1]
-      delays[2] <= ins[2]
-      delays[3] <= ins[3]
-    else : when shift : 
-        delays[0] <= ins[0]
-        delays[1] <= delays[0]
-        delays[2] <= delays[1]
-        delays[3] <= delays[2]
-    out <= delays[3]