New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 14 insertions, 14 deletions

diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 02ae03b5..eb2a0f34 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -12,19 +12,19 @@ circuit RegisterVecShift :
     reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
-      T_33[0] := UInt<4>(0)
-      T_33[1] := UInt<4>(0)
-      T_33[2] := UInt<4>(0)
-      T_33[3] := UInt<4>(0)
-      delays := T_33
+      T_33[0] <= UInt<4>(0)
+      T_33[1] <= UInt<4>(0)
+      T_33[2] <= UInt<4>(0)
+      T_33[3] <= UInt<4>(0)
+      delays <= T_33
     when load : 
-      delays[0] := ins[0]
-      delays[1] := ins[1]
-      delays[2] := ins[2]
-      delays[3] := ins[3]
+      delays[0] <= ins[0]
+      delays[1] <= ins[1]
+      delays[2] <= ins[2]
+      delays[3] <= ins[3]
     else : when shift : 
-        delays[0] := ins[0]
-        delays[1] := delays[0]
-        delays[2] := delays[1]
-        delays[3] := delays[2]
-    out := delays[3]
+        delays[0] <= ins[0]
+        delays[1] <= delays[0]
+        delays[2] <= delays[1]
+        delays[3] <= delays[2]
+    out <= delays[3]