diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/jacktest/RegisterVecShift.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/jacktest/RegisterVecShift.fir')
| -rw-r--r-- | test/passes/jacktest/RegisterVecShift.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index 61376a62..f138d00a 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -9,7 +9,8 @@ circuit RegisterVecShift : input shift : UInt<1> input ins : UInt<4>[4] - reg delays : UInt<4>[4],clk,reset,delays + reg delays : UInt<4>[4],clk with : + reset => (reset,delays) when reset : wire T_33 : UInt<4>[4] T_33[0] <= UInt<4>(0) |