Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

1 files changed, 3 insertions, 1 deletions

diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index d24bc383..cca645d1 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,11 +3,13 @@
 circuit RegisterVecShift : 
   module RegisterVecShift : 
     input load : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4]
+    reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] := UInt<4>(0)