diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/Mul.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/Mul.fir')
| -rw-r--r-- | test/passes/jacktest/Mul.fir | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir deleted file mode 100644 index 370c84a7..00000000 --- a/test/passes/jacktest/Mul.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Mul : - module Mul : - input x : UInt<2> - input y : UInt<2> - output z : UInt<4> - - wire tbl : UInt<4>[16] - tbl[0] <= UInt<4>(0) - tbl[1] <= UInt<4>(0) - tbl[2] <= UInt<4>(0) - tbl[3] <= UInt<4>(0) - tbl[4] <= UInt<4>(0) - tbl[5] <= UInt<4>(1) - tbl[6] <= UInt<4>(2) - tbl[7] <= UInt<4>(3) - tbl[8] <= UInt<4>(0) - tbl[9] <= UInt<4>(2) - tbl[10] <= UInt<4>(4) - tbl[11] <= UInt<4>(6) - tbl[12] <= UInt<4>(0) - tbl[13] <= UInt<4>(3) - tbl[14] <= UInt<4>(6) - tbl[15] <= UInt<4>(9) - node T_42 = shl(x, 2) - node T_43 = or(T_42, y) - node T_44 = tbl[T_43] - z <= T_44 |