diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/MemorySearch.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/MemorySearch.fir')
| -rw-r--r-- | test/passes/jacktest/MemorySearch.fir | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index be6b3274..1e07596c 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -10,26 +10,26 @@ circuit MemorySearch : output done : UInt<1> reg index : UInt<3>,clk,reset - onreset index := UInt<3>(0) + onreset index <= UInt<3>(0) wire elts : UInt<4>[7] - elts[0] := UInt<4>(0) - elts[1] := UInt<4>(4) - elts[2] := UInt<4>(15) - elts[3] := UInt<4>(14) - elts[4] := UInt<4>(2) - elts[5] := UInt<4>(5) - elts[6] := UInt<4>(13) + elts[0] <= UInt<4>(0) + elts[1] <= UInt<4>(4) + elts[2] <= UInt<4>(15) + elts[3] <= UInt<4>(14) + elts[4] <= UInt<4>(2) + elts[5] <= UInt<4>(5) + elts[6] <= UInt<4>(13) infer accessor elt = elts[index] node T_35 = not(en) node T_36 = eq(elt, target) node T_37 = eq(index, UInt<3>(7)) node T_38 = or(T_36, T_37) node end = and(T_35, T_38) - when en : index := UInt<1>(0) + when en : index <= UInt<1>(0) else : node T_39 = not(end) when T_39 : node T_40 = addw(index, UInt<1>(1)) - index := T_40 - done := end - address := index + index <= T_40 + done <= end + address <= index |