diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/LFSR16.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/LFSR16.fir')
| -rw-r--r-- | test/passes/jacktest/LFSR16.fir | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir deleted file mode 100644 index b3fb05cc..00000000 --- a/test/passes/jacktest/LFSR16.fir +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit LFSR16 : - module LFSR16 : - output out : UInt<16> - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - - reg res : UInt<16>,clk with : - reset => (reset,UInt<16>(1)) - when inc : - node T_16 = bits(res, 0, 0) - node T_17 = bits(res, 2, 2) - node T_18 = xor(T_16, T_17) - node T_19 = bits(res, 3, 3) - node T_20 = xor(T_18, T_19) - node T_21 = bits(res, 5, 5) - node T_22 = xor(T_20, T_21) - node T_23 = bits(res, 15, 1) - node T_24 = cat(T_22, T_23) - res <= T_24 - out <= res |