diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/LFSR16.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/LFSR16.fir')
| -rw-r--r-- | test/passes/jacktest/LFSR16.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir index b8e31e99..770ac3e6 100644 --- a/test/passes/jacktest/LFSR16.fir +++ b/test/passes/jacktest/LFSR16.fir @@ -8,7 +8,7 @@ circuit LFSR16 : input reset : UInt<1> reg res : UInt<16>,clk,reset - onreset res := UInt<16>(1) + onreset res <= UInt<16>(1) when inc : node T_16 = bit(res, 0) node T_17 = bit(res, 2) @@ -19,5 +19,5 @@ circuit LFSR16 : node T_22 = xor(T_20, T_21) node T_23 = bits(res, 15, 1) node T_24 = cat(T_22, T_23) - res := T_24 - out := res + res <= T_24 + out <= res |