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authorazidar2016-01-07 17:15:31 -0800
committerazidar2016-01-16 14:28:18 -0800
commit4569194392122ae4715549b2f0b9fffff051b278 (patch)
treeecd079cefa6fb69d1f8c75bc0e75e38599bc0da4 /test/passes/jacktest/LFSR16.fir
parent2d583abda146dad8e0260928dcb19ad7136216b6 (diff)
Fixed a bunch of tests, and minor bugs
Diffstat (limited to 'test/passes/jacktest/LFSR16.fir')
-rw-r--r--test/passes/jacktest/LFSR16.fir3
1 files changed, 1 insertions, 2 deletions
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index 770ac3e6..a4052623 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -7,8 +7,7 @@ circuit LFSR16 :
input clk : Clock
input reset : UInt<1>
- reg res : UInt<16>,clk,reset
- onreset res <= UInt<16>(1)
+ reg res : UInt<16>,clk,reset,UInt<16>(1)
when inc :
node T_16 = bit(res, 0)
node T_17 = bit(res, 2)