Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 24 deletions

diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
deleted file mode 100644
index 9927e83f..00000000
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit EnableShiftRegister : 
-  module EnableShiftRegister : 
-    input in : UInt<4>
-    input clk : Clock
-    input reset : UInt<1>
-    output out : UInt<4>
-    input shift : UInt<1>
-    
-    reg r0 : UInt<4>,clk with :
-       reset => (reset,UInt<4>(0))
-    reg r1 : UInt<4>,clk with :
-       reset => (reset,UInt<4>(0))
-    reg r2 : UInt<4>,clk with :
-       reset => (reset,UInt<4>(0))
-    reg r3 : UInt<4>,clk with :
-       reset => (reset,UInt<4>(0))
-    when shift : 
-      r0 <= in
-      r1 <= r0
-      r2 <= r1
-      r3 <= r2
-    out <= r3