diff options
| author | azidar | 2016-01-07 17:15:31 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:18 -0800 |
| commit | 4569194392122ae4715549b2f0b9fffff051b278 (patch) | |
| tree | ecd079cefa6fb69d1f8c75bc0e75e38599bc0da4 /test/passes/jacktest/EnableShiftRegister.fir | |
| parent | 2d583abda146dad8e0260928dcb19ad7136216b6 (diff) | |
Fixed a bunch of tests, and minor bugs
Diffstat (limited to 'test/passes/jacktest/EnableShiftRegister.fir')
| -rw-r--r-- | test/passes/jacktest/EnableShiftRegister.fir | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir index 7937d37f..d7e91665 100644 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ b/test/passes/jacktest/EnableShiftRegister.fir @@ -8,14 +8,10 @@ circuit EnableShiftRegister : output out : UInt<4> input shift : UInt<1> - reg r0 : UInt<4>,clk,reset - onreset r0 <= UInt<4>(0) - reg r1 : UInt<4>,clk,reset - onreset r1 <= UInt<4>(0) - reg r2 : UInt<4>,clk,reset - onreset r2 <= UInt<4>(0) - reg r3 : UInt<4>,clk,reset - onreset r3 <= UInt<4>(0) + reg r0 : UInt<4>,clk,reset,UInt<4>(0) + reg r1 : UInt<4>,clk,reset,UInt<4>(0) + reg r2 : UInt<4>,clk,reset,UInt<4>(0) + reg r3 : UInt<4>,clk,reset,UInt<4>(0) when shift : r0 <= in r1 <= r0 |
