diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/jacktest/Counter.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/jacktest/Counter.fir')
| -rw-r--r-- | test/passes/jacktest/Counter.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir index a04ddf2f..db2b5d62 100644 --- a/test/passes/jacktest/Counter.fir +++ b/test/passes/jacktest/Counter.fir @@ -9,10 +9,10 @@ circuit Counter : input amt : UInt<4> reg T_13 : UInt<8>,clk,reset - onreset T_13 := UInt<8>(0) + onreset T_13 <= UInt<8>(0) when inc : node T_14 = addw(T_13, amt) node T_15 = gt(T_14, UInt<8>(255)) node T_16 = mux(T_15, UInt<1>(0), T_14) - T_13 := T_16 - tot := T_13 + T_13 <= T_16 + tot <= T_13 |