diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/jacktest/ComplexAssign.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/jacktest/ComplexAssign.fir')
| -rw-r--r-- | test/passes/jacktest/ComplexAssign.fir | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir deleted file mode 100644 index 9ce51652..00000000 --- a/test/passes/jacktest/ComplexAssign.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ComplexAssign : - module ComplexAssign : - input in : {re : UInt<10>, im : UInt<10>} - output out : {re : UInt<10>, im : UInt<10>} - input e : UInt<1> - when e : - wire T_18 : {re : UInt<10>, im : UInt<10>} - T_18 <= in - out.re <= T_18.re - out.im <= T_18.im - else : - out.re <= UInt<1>(0) - out.im <= UInt<1>(0) |