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| author | jackbackrack | 2015-05-20 03:52:53 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-05-20 03:52:53 -0700 |
| commit | 994fc58aa9a65eb4a5e287e121ee2e77d91db403 (patch) | |
| tree | 5a75bfd8f4bd0040e577e20c928d2ee5bc56924b /test/passes/jacktest/ComplexAssign.fir | |
| parent | f98ef93a1562357412fd1fce4b1f453f8a33572a (diff) | |
| parent | 92e7da031a14df41ee0cab13a4a63b472fbdb5e1 (diff) | |
merge
Diffstat (limited to 'test/passes/jacktest/ComplexAssign.fir')
| -rw-r--r-- | test/passes/jacktest/ComplexAssign.fir | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir new file mode 100644 index 00000000..8e508d7d --- /dev/null +++ b/test/passes/jacktest/ComplexAssign.fir @@ -0,0 +1,15 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! +circuit ComplexAssign : + module ComplexAssign : + input in : {re : UInt<10>, im : UInt<10>} + output out : {re : UInt<10>, im : UInt<10>} + input e : UInt<1> + when e : + wire T_18 : {re : UInt<10>, im : UInt<10>} + T_18 := in + out.re := T_18.re + out.im := T_18.im + else : + out.re := UInt<1>(0) + out.im := UInt<1>(0) |