Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass

8 files changed, 189 insertions, 0 deletions

diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
new file mode 100644
index 00000000..c41794e3
--- /dev/null
+++ b/test/passes/inline-indexers/bundle-vecs.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+; CHECK: Expand Indexed Connects
+circuit top :
+   module top :
+      wire i : UInt
+      i := UInt(1)
+      wire j : UInt
+      j := UInt(1)
+
+      wire a : { x : UInt<32>, flip y : UInt<32> }[2]
+      a[0].x := UInt(1)
+      a[0].y := UInt(1)
+      a[1].x := UInt(1)
+      a[1].y := UInt(1)
+      ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32>
+      ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32>
+      ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32>
+      ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32>
+
+
+      infer accessor b = a[i]
+      ; CHECK: wire b{{[_$]+}}x : UInt<32>
+      ; CHECK: wire b{{[_$]+}}y : UInt<32>
+      ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: node i_1 = i
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: node i_2 = i
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
+      j := b.x
+      b.y := UInt(1)
+      
+; CHECK: Finished Expand Indexed Connects
+
diff --git a/test/passes/inline-indexers/init-vecs.fir b/test/passes/inline-indexers/init-vecs.fir
new file mode 100644
index 00000000..7d64a117
--- /dev/null
+++ b/test/passes/inline-indexers/init-vecs.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; XFAIL: *
+
+; CHECK: Expand Indexed Connects
+circuit top :
+   module top :
+      wire outs : UInt<32>[2][1]
+      outs[0][0] := UInt(1)
+      outs[0][1] := UInt(1)
+
+      write accessor out = outs[UInt(0)]
+      out[0] := UInt(1)
+
+; CHECK: Done!
+
+
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
new file mode 100644
index 00000000..ca65977b
--- /dev/null
+++ b/test/passes/inline-indexers/simple.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      output o : UInt
+      wire m : UInt<32>[2]
+      wire i : UInt
+      m[0] := UInt("h1")
+      m[1] := UInt("h1")
+      i := UInt("h1")
+      infer accessor a = m[i] 
+      o := a
+
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
new file mode 100644
index 00000000..a334b626
--- /dev/null
+++ b/test/passes/inline-indexers/simple2.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      output o1 : UInt
+      output o2 : UInt
+      wire m : UInt<32>[2]
+      wire i : UInt
+      m[0] := UInt("h1")
+      m[1] := UInt("h1")
+      i := UInt("h1")
+      infer accessor a = m[i] 
+      o1 := a
+      o2 := a
+
+;CHECK: wire a : UInt<32>
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: wire a_1 : UInt<32>
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_1 := m$1
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
new file mode 100644
index 00000000..fd8d1418
--- /dev/null
+++ b/test/passes/inline-indexers/simple3.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      input in : UInt<32>
+      input i : UInt<1>
+      wire m : UInt<32>[2]
+      m[0] := UInt("h1")
+      m[1] := UInt("h1")
+      infer accessor a = m[i] 
+      a := in
+
+;CHECK: wire a : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a
+
+
+
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
new file mode 100644
index 00000000..dce8f26f
--- /dev/null
+++ b/test/passes/inline-indexers/simple4.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      input in : {x : UInt<32>, y : UInt<32>}
+      input i : UInt<1>
+      wire m : {x : UInt<32>, y : UInt<32>}[2]
+      m[0].x := UInt("h1")
+      m[0].y := UInt("h1")
+      m[1].x := UInt("h1")
+      m[1].y := UInt("h1")
+      infer accessor a = m[i] 
+      a.x := in.x
+
+;CHECK: wire a$x : UInt<32>
+;CHECK: node i_1 = i
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x
+;CHECK: a$x := in$x
+;CHECK: Finished Inline Indexers
+;CHECK: Done!
+
+
+
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
new file mode 100644
index 00000000..8cd7bec1
--- /dev/null
+++ b/test/passes/inline-indexers/simple5.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      output o : UInt
+      o := UInt(1)
+      wire m : UInt<32>[2]
+      wire i : UInt
+      m[0] := UInt("h1")
+      m[1] := UInt("h1")
+      i := UInt("h1")
+      when i  :
+         infer accessor a = m[i] 
+         o := a
+
+;CHECK: when i :
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: Finished Inline Indexers
+;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
new file mode 100644
index 00000000..98b28611
--- /dev/null
+++ b/test/passes/inline-indexers/simple6.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Inline Indexers
+circuit top :
+   module top :
+      input value : UInt<32>
+      input in : {x : UInt<32>, y : UInt<32>}
+      wire m :{x : UInt<32>, y : UInt<32>}[2][2] 
+      wire i : UInt
+
+      m[0][0] := in
+      m[1][0] := in
+      m[0][1] := in
+      m[1][1] := in
+      i := UInt("h1")
+
+      write accessor a = m[i] 
+      write accessor b = a[i] 
+      b.x := value
+
+;CHECK: a := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+
+
+
+;CHECK: Done!