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authorazidar2015-10-26 15:12:42 -0700
committerazidar2016-01-16 14:28:16 -0800
commit50ef3c4aa6c0ce8edb3f9d3fa7ac6bb5d081de7f (patch)
treef46024cd2582c8a48826a6c2113853abbc4f7e3c /test/passes/inline-indexers/simple6.fir
parent6a3a56d2870f2ba87854076857b4aee2909f94b8 (diff)
WIP need to correctly output readwrite ports
Diffstat (limited to 'test/passes/inline-indexers/simple6.fir')
-rw-r--r--test/passes/inline-indexers/simple6.fir20
1 files changed, 10 insertions, 10 deletions
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
index e94efc7a..b177fba2 100644
--- a/test/passes/inline-indexers/simple6.fir
+++ b/test/passes/inline-indexers/simple6.fir
@@ -20,25 +20,25 @@ circuit top :
write accessor b = a[j]
b.x := value
-;CHECK: wire b$x_1 : UInt<32>
+;CHECK: wire b$x_2 : UInt<32>
;CHECK: node j_1 = j
;CHECK: when eqv(j_1, UInt("h0")) :
-;CHECK: wire a$0$x_1 : UInt<32>
+;CHECK: wire a$0$x_2 : UInt<32>
;CHECK: node i_1 = i
;CHECK: when eqv(i_1, UInt("h0")) :
-;CHECK: m$0$0$x := a$0$x_1
+;CHECK: m$0$0$x := a$0$x_2
;CHECK: when eqv(i_1, UInt("h1")) :
-;CHECK: m$1$0$x := a$0$x_1
-;CHECK: a$0$x_1 := b$x_1
+;CHECK: m$1$0$x := a$0$x_2
+;CHECK: a$0$x_2 := b$x_2
;CHECK: when eqv(j_1, UInt("h1")) :
-;CHECK: wire a$1$x_1 : UInt<32>
+;CHECK: wire a$1$x_2 : UInt<32>
;CHECK: node i_2 = i
;CHECK: when eqv(i_2, UInt("h0")) :
-;CHECK: m$0$1$x := a$1$x_1
+;CHECK: m$0$1$x := a$1$x_2
;CHECK: when eqv(i_2, UInt("h1")) :
-;CHECK: m$1$1$x := a$1$x_1
-;CHECK: a$1$x_1 := b$x_1
-;CHECK: b$x_1 := value
+;CHECK: m$1$1$x := a$1$x_2
+;CHECK: a$1$x_2 := b$x_2
+;CHECK: b$x_2 := value