diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/inline-indexers/simple3.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/inline-indexers/simple3.fir')
| -rw-r--r-- | test/passes/inline-indexers/simple3.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir index b6a7616c..1ef4c192 100644 --- a/test/passes/inline-indexers/simple3.fir +++ b/test/passes/inline-indexers/simple3.fir @@ -6,14 +6,14 @@ circuit top : input in : UInt<32> input i : UInt<1> wire m : UInt<32>[2] - m[0] := UInt("h1") - m[1] := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") infer accessor a = m[i] - a := in + a <= in ;CHECK: wire a_2 : UInt<32> -;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_2 -;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_2 +;CHECK: when eqv(i_1, UInt("h0")) : m$0 <= a_2 +;CHECK: when eqv(i_1, UInt("h1")) : m$1 <= a_2 |