diff options
| author | azidar | 2015-10-26 15:12:42 -0700 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:16 -0800 |
| commit | 50ef3c4aa6c0ce8edb3f9d3fa7ac6bb5d081de7f (patch) | |
| tree | f46024cd2582c8a48826a6c2113853abbc4f7e3c /test/passes/inline-indexers/simple3.fir | |
| parent | 6a3a56d2870f2ba87854076857b4aee2909f94b8 (diff) | |
WIP need to correctly output readwrite ports
Diffstat (limited to 'test/passes/inline-indexers/simple3.fir')
| -rw-r--r-- | test/passes/inline-indexers/simple3.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir index 688958a0..b6a7616c 100644 --- a/test/passes/inline-indexers/simple3.fir +++ b/test/passes/inline-indexers/simple3.fir @@ -11,9 +11,9 @@ circuit top : infer accessor a = m[i] a := in -;CHECK: wire a_1 : UInt<32> -;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1 -;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1 +;CHECK: wire a_2 : UInt<32> +;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_2 +;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_2 |