diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/inline-indexers/bundle-vecs.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/inline-indexers/bundle-vecs.fir')
| -rw-r--r-- | test/passes/inline-indexers/bundle-vecs.fir | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir index f4fc609d..9a28fc3e 100644 --- a/test/passes/inline-indexers/bundle-vecs.fir +++ b/test/passes/inline-indexers/bundle-vecs.fir @@ -4,15 +4,15 @@ circuit top : module top : wire i : UInt - i := UInt(1) + i <= UInt(1) wire j : UInt - j := UInt(1) + j <= UInt(1) wire a : { x : UInt<32>, flip y : UInt<32> }[2] - a[0].x := UInt(1) - a[0].y := UInt(1) - a[1].x := UInt(1) - a[1].y := UInt(1) + a[0].x <= UInt(1) + a[0].y <= UInt(1) + a[1].x <= UInt(1) + a[1].y <= UInt(1) ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> @@ -22,14 +22,14 @@ circuit top : infer accessor b = a[i] ; CHECK: wire b{{[_$]+}}x_2 : UInt<32> ; CHECK: node i_1 = i - ; CHECK: b{{[_$]+}}x_2 := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: b{{[_$]+}}x_2 <= a{{[_$]+}}0{{[_$]+}}x + ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 <= a{{[_$]+}}1{{[_$]+}}x ; CHECK: wire b{{[_$]+}}y_2 : UInt<32> ; CHECK: node i_2 = i - ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_2 - ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_2 - j := b.x - b.y := UInt(1) + ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y <= b{{[_$]+}}y_2 + ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y <= b{{[_$]+}}y_2 + j <= b.x + b.y <= UInt(1) ; CHECK: Finished Inline Indexers ; CHECK: Done! |