diff options
| author | azidar | 2015-10-26 15:12:42 -0700 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:16 -0800 |
| commit | 50ef3c4aa6c0ce8edb3f9d3fa7ac6bb5d081de7f (patch) | |
| tree | f46024cd2582c8a48826a6c2113853abbc4f7e3c /test/passes/inline-indexers/bundle-vecs.fir | |
| parent | 6a3a56d2870f2ba87854076857b4aee2909f94b8 (diff) | |
WIP need to correctly output readwrite ports
Diffstat (limited to 'test/passes/inline-indexers/bundle-vecs.fir')
| -rw-r--r-- | test/passes/inline-indexers/bundle-vecs.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir index 28826056..f4fc609d 100644 --- a/test/passes/inline-indexers/bundle-vecs.fir +++ b/test/passes/inline-indexers/bundle-vecs.fir @@ -20,14 +20,14 @@ circuit top : infer accessor b = a[i] - ; CHECK: wire b{{[_$]+}}x_1 : UInt<32> + ; CHECK: wire b{{[_$]+}}x_2 : UInt<32> ; CHECK: node i_1 = i - ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x - ; CHECK: wire b{{[_$]+}}y_1 : UInt<32> + ; CHECK: b{{[_$]+}}x_2 := a{{[_$]+}}0{{[_$]+}}x + ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: wire b{{[_$]+}}y_2 : UInt<32> ; CHECK: node i_2 = i - ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1 - ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1 + ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_2 + ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_2 j := b.x b.y := UInt(1) |