diff options
| author | azidar | 2015-09-29 15:49:52 -0700 |
|---|---|---|
| committer | azidar | 2015-09-29 15:49:52 -0700 |
| commit | 2a9bd217e6d8e519bc78f66e44502d77fa9cdc1d (patch) | |
| tree | 8c74300cbf7eaf289fc0121c1fdd3efb0b378b07 /test/passes/inline-indexers/bundle-vecs.fir | |
| parent | d380b8cfd11d2fe1231774f7b9492aff959bb279 (diff) | |
Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
Diffstat (limited to 'test/passes/inline-indexers/bundle-vecs.fir')
| -rw-r--r-- | test/passes/inline-indexers/bundle-vecs.fir | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir new file mode 100644 index 00000000..c41794e3 --- /dev/null +++ b/test/passes/inline-indexers/bundle-vecs.fir @@ -0,0 +1,35 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Expand Indexed Connects +circuit top : + module top : + wire i : UInt + i := UInt(1) + wire j : UInt + j := UInt(1) + + wire a : { x : UInt<32>, flip y : UInt<32> }[2] + a[0].x := UInt(1) + a[0].y := UInt(1) + a[1].x := UInt(1) + a[1].y := UInt(1) + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> + + + infer accessor b = a[i] + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x + ; CHECK: node i_1 = i + ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: node i_2 = i + ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y + j := b.x + b.y := UInt(1) + +; CHECK: Finished Expand Indexed Connects + |