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| author | azidar | 2015-04-23 17:53:29 -0700 |
|---|---|---|
| committer | azidar | 2015-04-23 17:53:29 -0700 |
| commit | 32148a311e06e8028b95da4bd8b1c888b5d8220f (patch) | |
| tree | d2c0fc6bf281d907746079b31b0feddf542f277b /test/passes/initialize-regs/bundle-init.fir | |
| parent | 3862865b8c70dd21e1a436dd79cfd165bebe5f43 (diff) | |
Not finished commmit
Diffstat (limited to 'test/passes/initialize-regs/bundle-init.fir')
| -rw-r--r-- | test/passes/initialize-regs/bundle-init.fir | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir new file mode 100644 index 00000000..7e9af8df --- /dev/null +++ b/test/passes/initialize-regs/bundle-init.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s +; CHECK: Done! +circuit top : + module A : + reg r : { x : UInt, flip y : UInt} + wire a : UInt + wire b : UInt + wire w : { x : UInt, flip y : UInt} + + r.x := a + r.y := b + on-reset r := w + +; CHECK: reg r : { x, flip y} +; CHECK: r.x := a +; CHECK: r.y := b +; CHECK: when reset : +; CHECK: r.x := w.x +; CHECK: w.y := r.y + + |
