diff options
| author | azidar | 2015-04-27 11:14:06 -0700 |
|---|---|---|
| committer | azidar | 2015-04-27 11:14:06 -0700 |
| commit | 2d2120a05549a5d31072aa792dc96fb7e6e7c629 (patch) | |
| tree | 900e95aecdd6af6dc0e62a889ab2b81c8b4d2f80 /test/passes/initialize-regs/bundle-init.fir | |
| parent | 55a4ce521e06aa51aa005eb37c47918c0eece57c (diff) | |
Added on-reset
Diffstat (limited to 'test/passes/initialize-regs/bundle-init.fir')
| -rw-r--r-- | test/passes/initialize-regs/bundle-init.fir | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir deleted file mode 100644 index 7e9af8df..00000000 --- a/test/passes/initialize-regs/bundle-init.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module A : - reg r : { x : UInt, flip y : UInt} - wire a : UInt - wire b : UInt - wire w : { x : UInt, flip y : UInt} - - r.x := a - r.y := b - on-reset r := w - -; CHECK: reg r : { x, flip y} -; CHECK: r.x := a -; CHECK: r.y := b -; CHECK: when reset : -; CHECK: r.x := w.x -; CHECK: w.y := r.y - - |