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| author | azidar | 2015-03-04 16:25:25 -0800 |
|---|---|---|
| committer | azidar | 2015-03-04 16:25:25 -0800 |
| commit | 6ad6267d26b52258f6e0d4d004aeb5f36856cf95 (patch) | |
| tree | 16aad9875b1f58dc0cc2a5cd59091e89d57a0861 /test/passes/initialize-register/when.fir | |
| parent | 355749c83d2066f1a149333ed762a7945d405076 (diff) | |
Finished infer-types pass
Diffstat (limited to 'test/passes/initialize-register/when.fir')
| -rw-r--r-- | test/passes/initialize-register/when.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir index 4e2bef79..4e0690d8 100644 --- a/test/passes/initialize-register/when.fir +++ b/test/passes/initialize-register/when.fir @@ -6,7 +6,7 @@ input a : UInt(16) input b : UInt(16) output z : UInt - when greater(1, 2) : + when gt(1, 2) : reg r1: UInt r1.init := UInt(12) ; CHECK: wire [[R1:gen[0-9]*]] : UInt |