diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | d696dd01de8a1a83a376c719490f475be991f387 (patch) | |
| tree | ca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/passes/infer-widths | |
| parent | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/passes/infer-widths')
| -rw-r--r-- | test/passes/infer-widths/dsh.fir | 3 | ||||
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 6b683e56..08396978 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -11,6 +11,9 @@ circuit top : wire b : SInt wire c : UInt wire d : SInt + x := UInt(1) + y := UInt(1) + z := SInt(1) a := dshl(x,y) b := dshl(z,y) diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 590515e7..6a50ae77 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -4,12 +4,16 @@ circuit top : module top : wire e : UInt<30> + e := UInt(1) reg y : UInt y := e wire a : UInt<20> + a := UInt(1) wire b : UInt<10> + b := UInt(1) wire c : UInt + c := UInt(1) wire z : UInt z := mux(c,a,b) |