diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/infer-widths/simple.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/infer-widths/simple.fir')
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir deleted file mode 100644 index 63b31a32..00000000 --- a/test/passes/infer-widths/simple.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cTwd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire e : UInt<30> - e <= UInt(1) - reg y : UInt,clk with : - reset => (reset,y) - y <= e - - wire a : UInt<20> - a <= UInt(1) - wire b : UInt<10> - b <= UInt(1) - wire c : UInt - c <= UInt(1) - wire z : UInt - - z <= mux(c,a,b) - - - -; CHECK: Finished Infer Widths -; CHECK: Done! - |