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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-14 11:29:55 -0700
commit271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch)
tree8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/infer-widths/simple.fir
parent0bfb3618b654a4082cc2780887b3ca32e374f455 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/infer-widths/simple.fir')
-rw-r--r--test/passes/infer-widths/simple.fir4
1 files changed, 3 insertions, 1 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 6a50ae77..1b588c0e 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -3,9 +3,11 @@
;CHECK: Infer Widths
circuit top :
module top :
+ input clk : Clock
+ input reset : UInt<1>
wire e : UInt<30>
e := UInt(1)
- reg y : UInt
+ reg y : UInt,clk,reset
y := e
wire a : UInt<20>