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| author | azidar | 2015-04-23 11:46:47 -0700 |
|---|---|---|
| committer | azidar | 2015-04-23 11:46:47 -0700 |
| commit | accb511cb37ce595d28bb3feefe5be79bc6ae303 (patch) | |
| tree | 1a1d2212c2d04b773238fb5b0c7eb9368df83b9b /test/passes/infer-widths/simple.fir | |
| parent | aa5eb968b837a4c35c5361b5f567411766c52184 (diff) | |
| parent | 7f8758420a2a46d7cf19441e9fbd1dba82cae612 (diff) | |
Merge branch 'master' into parser
Diffstat (limited to 'test/passes/infer-widths/simple.fir')
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 432030d5..50eb5452 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTwd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : @@ -6,6 +6,14 @@ circuit top : wire e : UInt(30) reg y : UInt y := e + + wire a : UInt(20) + wire b : UInt(10) + wire c : UInt + wire z : UInt + + z := mux(c,Pad(a,?),Pad(b,?)) + ; CHECK: Finished Infer Widths |