diff options
| author | azidar | 2015-04-09 16:57:00 -0700 |
|---|---|---|
| committer | azidar | 2015-04-09 16:57:00 -0700 |
| commit | a604e0789a85d8b3c5d6def2f9860047f479b68a (patch) | |
| tree | ff2890d273f30155c52b610824a3ea632f2c12c6 /test/passes/infer-widths/simple.fir | |
| parent | 16b9cb55c7d3e546af7eee3528079c9ac9bb530b (diff) | |
Added more 'fake' tests. infer-widths now collects constraints
Diffstat (limited to 'test/passes/infer-widths/simple.fir')
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir new file mode 100644 index 00000000..f98d98da --- /dev/null +++ b/test/passes/infer-widths/simple.fir @@ -0,0 +1,13 @@ +; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s + +;CHECK: Infer Widths +circuit top : + module top : + wire e : UInt + wire x : UInt + reg y : UInt + y := mux-uu(e, UInt(1), equal-uu(gt-uu(x, x), UInt(0))) + + +; CHECK: Finished Infer Widths + |