diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/infer-widths/simple.fir | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/infer-widths/simple.fir')
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index e0d23c37..dc3007f9 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -7,7 +7,7 @@ circuit top : input reset : UInt<1> wire e : UInt<30> e <= UInt(1) - reg y : UInt,clk,reset + reg y : UInt,clk,reset,y y <= e wire a : UInt<20> @@ -23,4 +23,5 @@ circuit top : ; CHECK: Finished Infer Widths +; CHECK: Done! |