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| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-07 10:13:29 -0700 |
| commit | df4bae5c7a95d3a56f95d86212f083b7ba121da7 (patch) | |
| tree | af46f090557734528d9d29fcf499d73024c575ac /test/passes/infer-widths/dsh.fir | |
| parent | c8d1fc06443e81374b1af95e17e3ecbecf863700 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/passes/infer-widths/dsh.fir')
| -rw-r--r-- | test/passes/infer-widths/dsh.fir | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 6b683e56..08396978 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -11,6 +11,9 @@ circuit top : wire b : SInt wire c : UInt wire d : SInt + x := UInt(1) + y := UInt(1) + z := SInt(1) a := dshl(x,y) b := dshl(z,y) |